Si-Cheng Liu(劉思成), Xiao-Yan Tang(湯曉燕),3,Qing-Wen Song(宋慶文),3,?, Hao Yuan(袁昊),Yi-Meng Zhang(張藝蒙), Yi-Men Zhang(張義門(mén)),3, and Yu-Ming Zhang(張玉明),3

1Key Laboratory of Wide Band Gap Semiconductor Materials and Devices,Xidian University,Xi’an 710071,China

2School of Microelectronics,Xidian University,Xi’an 710071,China

3XiDian-WuHu Research Institute,WuHu 241000,China

Keywords: junction field-effect transistors,high temperature,4H-SiC,depletion-mode

1. Introduction

Aerospace, automotive, energy production, and other industrial systems are calling for electronics that can operate reliably in harsh environments, including high temperatures (above 300?C).[1]Due to the large bandgap, silicon carbide (SiC) materials not only shine in the field of highpower devices,[2–4]but also attract much attention for devices which can operate under harsh environment.[5]Over the past decade, significant progress has already been made in the high-temperature devices and integrated circuits(ICs). Hightemperature ICs based on metal-oxide-semiconductor fieldeffect transistors(MOSFETs),[6,7]bipolar junction transistors(BJTs),[8,9]and junction field-effect transistors (JFETs)[10,11]have already been reported. High stability of threshold(VTH)within a wide temperature range and being free from oxide reliability problem give JFET based ICs very high robustness for harsh environment applications. Packaged 4HSiC JFET-based logic ICs with two level interconnects are reported.[12]So far, 4H-SiC lateral trench JFETs (LTJFETs)operating at 450?C have also been developed for harsh environment applications.[13]More recently, for reducing power loss, 400?C normally-on and normally-off operation of nchannel and p-channel junction field-effect transistors(JFETs)or complementary JFET(CJFET)fabricated by ion implantation into a common high-purity semi-insulating silicon carbide(SiC)substrate has been demonstrated.[14,15]

Expect for LTJFETs and CJFETs, the most common reported JFET ICs are based on 4H-SiC p-type wafer, and the backside metallization to the p-type substrate facilitates more direct control of the electrical potential of the p-type epilayer immediately beneath the JFET n-channel.[10–12]However,the backside contact needs extra diffusion barrier metallization(such as TaSi2/Pt metallization) to prevent the migration of bond pad Au and atmospheric oxygen toward the ohmic contact/SiC interface, otherwise devices will lose their backside contact in high temperature environment.[16,17]What’s more,the inter-metallic mixing between the introduced diffusion barrier system and the underlying ohmic contact metallization is another dominant failure mechanism at high temperature. It will reduce the challenges of high temperature packaging and long-term stability of ICs by bringing the back-side body contact to front side, as shown in Fig.1. In this work, 4H-SiC n-channel LJFETs based on n-type wafer are demonstrated to operate with well-behaved characteristics at temperatures ranging from room temperature to 400?C.

2. Device fabrication

Figure 1 shows the schematic cross section of a fabricated 4H-SiC lateral JFET structure. The devices were fabricated using customer-ordered heavily doped n-type 4H-SiC wafers with three different epi-layers. The thickness and doping concentration of individual epilayers are given in Fig.1.The fabrication process starts from the dry etching of the p+gate finger mesa structure with depth of 0.3 μm by inductively coupled plasma(ICP)etching. Then,to reduce the gateto-source and gate-to-drain series resistance (RS/D), nitrogen(N) ions are implanted with a box profile. To achieve better source/drain ohmic contact,high temperature nitrogen implant is also used to form the n+contact area to the source and drain,with doses of 7.3×1014, 5.7×1014and 4.0×1014cm?2, respectively. Then the second ICP etching with depth of 0.8μm was performed to form the active region and to isolate the devices. In order to form p+ohmic contact region in the bulk layer, a series of high temperature aluminum (Al+) implants were also performed with doses of 8.6×1014, 5.6×1014and 3.3×1014cm?2,respectively. The implantation annealing was performed at 1700?C for 30 min with carbon film protection.After sacrificial oxidation,the surface passivation was accomplished by a three-hour oxidation process at 1100?C,followed by a 1-μm PECVD SiO2layer. After the surface passivation layer opening, a 200 nm nickel (Ni) thin layer was sputtered in the contact regions and annealed to form the metal ohmic contacts. An 800-nm-thick layer of Al was deposited and patterned to form the metal interconnects. Finally,4-μm-thick Al metal was patterned for the pad. Figures 2(a) and 2(b) show the layout(not including the pad layer)and the optical image of a fabricated 4H-SiC lateral JFET with gate length L=6μm and gate width W =120μm. All the metal contacts are protected by the surface passivation layer for better device operating lifetime.

Fig.1. Schematic cross section of the fabricated 4H-SiC lateral JFET device.

The electrical properties of the devices were measured on-chip using a probe station(Cascade MPS150)and a digital ceramic hot plate to heat the samples from room temperature to 400?C in air. A semiconductor parameter analyzer (Agilent B1500A)was used to measure the current–voltage(I–V)characteristics of the devices. At each temperature point, the LJFET device and adjacent TLM structures are tested together.

Fig.2. (a)Layout and(b)optical micrograph of a fabricated device of a typical JFET with L=6μm and W =120μm.

3. Results and discussion

3.1. Ohmic contact characteristics at high temperature

Ohmic contact is a key step in achieving highperformance SiC LJFETs.In this work,on-wafer transmission line measurement (TLM) structures (consisting of six identical metal pads with area of 150×150 μm2and spacing d of 20, 40, 60, 80, 100μm)were used to extract specific contact resistance ρcand sheet resistance RSH.

The TLM structure in Fig.3(a)was used to measure the ρcof the Ni n+/p+contact (given n+contact resistance Rc)and the sheet resistance RSH.n+of the n+layer (given n+region resistance Rn+). The TLM structure in Fig.3(b)was used to measure the sheet resistance RSH.nof the light nitrogen(N)implanted layer (given gate-to-drain/gate-to-source series resistance RS/D). Figure 3(c) shows each extrinsic resistance component’s contribution to the parasitic resistance RParaof the device.

Figure 4(a) shows the 25?C on-wafer TLM I–V characteristics of both source/drain n-type and gate p-type ohmic contacts, along with the corresponding TLM fitting curves.For the source/drain n-type contacts,the ρcand the RSH.n+are 6.29×10?5Ω·cm2and 0.53 kΩ/□,respectively. For the gate p-type ohmic contact, the eliminate of the metallic contact’s Schottky barrier is beneficial for reducing the gate series resistance. The ρcand the RSHfor the gate p-type ohmic contact are 3.19×10?4Ω·cm2and 16.40 kΩ/□,respectively.

Figure 4(b)shows the on-wafer TLM I–V curves at different temperatures with contact spacing d=20μm. It is shown that both n-type and p-type contacts remain excellent ohmic behavior at temperature up to 400?C. At 400?C, due to increasing average electron kinetic energy,the n-type contacts ρcreduce to 3.95×10?6Ω·cm2. For the p-type ohmic contacts,the ρcslightly increases to 8.86×10?4Ω·cm2. Since the gate current is very small, it is enough to meet the demand. This result indicates that the employed metallic contact scheme can simultaneously form ohmic contact to both source/drain ntype and gate p-type regions with excellent high-temperature Ohmic characteristics up to 400?C.

Fig.3. Schematic of TLMs to measure(a)ρc between Ni metal and n+/p+ 4H-SiC along with the corresponding Rc, and RSH.n+ along with the corresponding Rn+. (b)Light doped N layer RSH.n along with the corresponding RS/D. (c)Schematic of extrinsic resistance components.The contributions to and equation for RPara are also given.

Fig.4. On-chip TLM I–V measurements of the source/drain n-type and gate p-type ohmic contacts characteristics: (a) 25 ?C I–V curves and TLM fitting curves(inset),(b)I–V curves at different temperatures with spacing d=20μm.

As described above in the device fabrication section, to minimize the gate-to-source and gate-to-drain series resistance influence, a light doped n-type layer between the gate and source/drain has been created using N+implantation. As shown in Fig.5(a),at room temperature this light n-type layer sheet resistance RSH.nis extracted from on-wafer TLM to be 2.83 kΩ/□,and much greater than n+source/drain layer sheet resistance RSH.n+of 0.53 kΩ/□. Compared with the reported light n-type layer sheet resistance data,[18]RSH.nin our work is effectively reduced by optimization of the dose of light nitrogen implants. As temperature increases to 400?C,the higher the doping concentration,the lower the dopant activation,and the ionized dopant concentration increase is compensated for by the mobility lowering,[19]therefore RSH.ngradually increases to 9.44 kΩ/□while RSH.n+swings to 0.48 kΩ/□.

Fig.5.Variation of(a)RSH for n+and n layer,(b)RPara and contribution of each component at different temperatures.

According to Fig.5(b), RParaof 17.56 kΩ·μm is obtained at 25?C, which is mainly contributed by RS/Dof 14.14 kΩ·μm, and the contribution of Rcto the total RParais only 10.41%. As temperature increases to 400?C,RParaincreases to 47.18 kΩ·μm and the contribution of Rcdecreases to 0.89%, which is dominated by the increase of RS/D. This result indicates that the light nitrogen implantation process is a very critical step for fabrication SiC JFETs in high temperature applications.

3.2. Electrical characterization at high temperature

Figures 6(a) and 6(b) show the typical drain-to-source current versus drain-to-source voltage(IDS–VDS)curves(output characteristics) of the fabricated 4H-SiC LJFET at room temperature and 400?C. The drain IDS–VDScharacteristics were measured at a body-to-source (VBS) bias of 0 V and a gate-to-source(VGS)bias of ?8 to 0 V with ?1 V steps. It can be seen that the fabricated 4H-SiC LJFET shows good transistor performance. At 25?C,this fabricated LJFET conducts 23.03μA/μm drain-to-source saturation current IDsatat VDSof 20 V,and VGSof 0 V,corresponding to a very large drain current density JDSof 7678 A/cm2by considering that the channel layer is 300 nm and the channel width is 120μm(for a crosssectional area of 3.6×10?7cm2). At 400?C, the developed device remains good transistor performance. As temperature increases to 400?C, IDsatdecreases to 7.47 μA/μm, which is mainly caused by the decrease of electron mobility with increasing temperature.

Fig.6. Typical measured drain IDS–VDS curves(output characteristics)for VBS=0 V(a)at 25 ?C and 400 ?C,and(b)for VGS=0 V at different temperatures of the fabricated 4H-SiC LJFET with L=6 μm and W =120μm at 25 ?C.

On-resistance Ronof the fabricated device is extracted at VDSof 0.5 V,VGSand VBSof 0 V.As shown in Fig.7,at room temperature,Ronis extracted to be 130.15 kΩ·μm,and mainly contributed by channel resistance RChanof 95.03 kΩ·μm or 73.02%. RParaof 17.56 kΩ·μm is contributed by Ronof only 13.49%. Considering RS/Dof the devices without light nitrogen implants can be estimated to be at least 79 kΩ·μm(it is assumed that the thickness and doping concentration in the gate-to-drain/gate-to-source region is the same as that in the channel region). RS/Dis significantly reduced by the adopted light nitrogen implants,thus RParais reduced greatly.As temperature increases to 400?C, caused by electron mobility lowering, Ronand RChanincrease up to 499.24 kΩ·μm and 401.14 kΩ·μm,respectively. The contribution of RParais around 10%within the measured temperature range(13.19%–9.28% at 25–250?C, respectively). This result indicates that RParais effectively reduced by the applied ohmic contacts and light nitrogen implants.

Fig.7. Variation of Ron at different temperatures. The contributions to Ron and the equation are also given.

Fig.8. Measured typical drain IDS–VGS curves(transfer characteristics)of the fabricated 4H-SiC LJFET with L=6 μm and W =120 μm at different temperatures for VSUB=0 V and VDS=20 V.

Figure 8 shows the typical transfer characteristics of the fabricated 4H-SiC LJFET at different temperatures for VDS=20 V and VBS=0 V. The VTHis extracted to be ?5.31 V, at 25?C. At 400?C, the VTHdecreases to ?7.06 V, which is affected by the decrease of built-in voltage and the increase of effective channel thickness.[20]The off-state current Iofffor VGS=?8 V and VDS=20 V is 2.44×10?3mA at room temperature, and increases up to 6.23×10?3mA as temperature increases to 400?C, due to the increasing intrinsic carrier concentration.[21]Ioffis significantly larger than the value theoretically predicted. The excessive Ioffis also reported by NASA.[22,23]We surmise that Ioffis caused by unexpected process failure,and further studies of this problem,which are well beyond the scope of this work,are warranted.

In the typical design of JFET ICs,VBSis not always biased at 0 V. As shown in Figs. 9(a) and 9(b), the JFET I–V curves have a dependence on the applied VBS,because the VBSmodifies the width of the depletion region at the p–n junction,decreasing the effective conducting channel thickness.At room temperature,as VBSdecreases to ?20 V,IDsatdecreases to 14.75μA/μm and VTHincreases to ?3.75 V.At 400?C,for VBS=?20 V, IDsatis 4.45 μA/μm and VTHis ?4.50 V. This result together with Fig.8 indicates that this device remains effective,and the normally-on operation under tested temperature and bias range is beneficial for circuit applications.

Fig.9. (a) The typical measured drain IDS–VDS curves at 25 ?C and 400 ?C for VGS = 0 V (output characteristics), and (b) the IDS–VGS curves for VDS = 20 V, with different VBS of the fabricated 4H-SiC LJFET for L=6μm and W =120μm.

As shown in Fig.10, the value of transconductance gmis extracted from the measured transfer characteristics by?IDsat/?VGSand normalized to the channel width of 120μm.The intrinsic transconductance gm.intis calculated using the equation shown in Fig.10. At 25?C, gmof 8.61 μS/μm for VGS=0 V is among the highest value in the reported devices with the similar structure.[11]The corresponding gm.int=10.14μS/μm indicates that the reduction caused by the RParais 15.12%. As temperature increases to 400?C,gmand gm.intgradually reduce to 2.35 and 2.66 μS/μm, respectively. The reduction caused by RParais around 10% at different temperatures (15.12%–11.61% at 25?C and 300?C, respectively).This result indicates that the improved gmis mainly due to the reduction of RPara.

Fig.10. The temperature dependence of gm and gm.int for the fabricated 4H-SiC LJFET at VGS=0 V with L=6μm and W =120μm.

As is shown in Fig.11, at room temperature, the output resistance r0is 5.01×104Ω,corresponding to an intrinsic gain gmr0of 51.79. Considering today’s silicon CMOS technology, gmr0of short-channel devices is between roughly 5 and 10,[24]it fully meets the demands. As temperature increases to 400?C,gmr0slightly decreases to 41.35 because the reduction in gmwith increasing temperature is compensated for by the increase of r0. These results indicate that the developed 4H-SiC LJFET is promising for high temperature electronic applications.

Fig.11. The temperature dependence of the normalized 4H-SiC LJFET performance parameters for VGS=0 V.

4. Conclusion and perspectives

Lateral depletion-mode 4H-SiC n-channel JFETs have been demonstrated to perform well at temperatures up to 400?C. The gate-to-source parasitic resistance is reduced to 17.56 kΩ·μm by optimized light N+implantation process,which is helpful for improving the transconductance up to 8.61 μS/μm at room temperature. At 400?C, the transconductance and intrinsic gain remain 2.35 μS/μm and 41.35.This work demonstrates that the developed 4H-SiC JFETs are promising for applications in high-temperature environments.