張玉岐，左致遠，闞 強，趙 佳,4

（1.山東大學 激光與紅外系統(tǒng)集成技術教育部重點實驗室，山東青島 266237；2.廈門市三安集成電路有限公司，福建廈門 361000；3.中國科學院半導體研究所，北京 100083；4.山東大學 信息科學與工程學院，山東青島 266237）

1 Introduction

Vertical Cavity Surface Emitting Lasers (VCSELs) are one of the most popular types of semiconductor lasers, and have a wide application range in the industry.It has the advantages of a low threshold, low power consumption, easy fabrication,high rate and low cost, and has become the core light source for short-range fiber optics data communications and optical sensing[1-4].Most of them use GaAs/AlGaAs materials operating at 850 nm.

Reliability is a key indicator of long-term use of semiconductor lasers and is very important for applications, and is the core problem of device development, design, fabrications and application[5-6].VCSELs had a field failure rate of ＜10 ppm/year over the past decade, thanks to the improvement of its design capacity and technological level, and the adoption of extensive preventive measures and screening measures[7-8].However, when a large number of VCSELs are used in the field[9], the system failure rate can still involve multiple unplanned failures per year when these failures are clustered in large data communication centers with thousands of links.Moreover, in data communication applications, the service life of devices is generally long,usually more than 10 years[10], which demands higher requirements on the reliability of VCSEL devices.Without proper device design, manufacturing and usage, these failure modes lead to high failure rates in oxide VCSELs.For the oxide VCSELs based on GaAs/AlGaAs materials, due to the inherent reasons of device material and structure design, there are potential reliability problems that have received great attention from the industry[11-13].

Therefore, we focus on the most widely used commercial oxide VCSELs[9]made from GaAs/AlGaAs materials in this paper.We expound the common causes of VCSEL failure from the perspectives of device design, manufacturing and external factors, the failure phenomena and mechanisms are summarized and analyzed, and puts forward some improvement suggestions and preventive measures.Through this, it can act as a reference for device R&D and production personnel when they encounter the same or similar situations to quickly and effectively understand their root causes and provide appropriate improvement measures.This will eventually help improve the reliability of the devices.

2 VCSEL structure

An oxide VCSELs structure is composed of a substrate, top and bottom Distributed Bragg Reflector (DBR), quantum wells (also called the active layer), an oxide layer and positive and negative contacts.The light output direction is perpendicular to the wafer surface, and most emit light at 850 nm.A schematic drawing of the oxide VCSEL structure is shown in Fig.1 (Color online).The substrate is usually n-type doped GaAs material.The epi layers are usually grown by Metal-Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy(MBE) on the substrate.The DBRs are multiple pairs of high and low refractive index materials(AlxGa1-xAs materials) grown alternately, where the high-index layer contains the low aluminum content wherexis typically 0.15-0.20.The low-index of the layer has a high aluminum where contentxis typically 0.8-1.0 for 850 nm VCSELs.

Fig.1 Schematic diagram of the oxide VCSEL structure[16]圖1 氧化型VCSEL的結構示意圖[16]

The quantum wells (usually 3-5 wells) are composed of GaAs/AlGaAs or AlGaAs/InGaAs materials.The oxide layer is AlGaAs with a higher Al concentration or AlAs materials that is located in the p-DBR above the quantum wells, and thickness generally 20-30 nm.It is necessary to etch a mesa structure and then perform selective wet oxidation to form the oxide aperture.This oxide aperture is used to confine current and light.Thus, the threshold current and optical loss can be effectively reduced, so the power conversion efficiency of VCSEL is improved, and the performance of VCSEL is greatly improved[14-15].

3 Common failure modes and analysis

3.1 VCSEL design

3.1.1 Materials system

For any semiconductor laser, the choice of materials system is key, especially the material of the quantum wells used to make the device, and the barrier that makes contact with the quantum well.The widely-used commercial oxide VCSELs are prepared by GaAs/AlGaAs epitaxial materials at present, due to the fact that GaAs and AlGaAs materials have a matched lattice and have a large refractive index difference, so the device has a small DBR thickness to get a high reflectivity and excellent performance, etc.It was found that dislocation is easily formed in GaAs/AlGaAs compound semiconductor materials[17].This may be due to the band gap energy of the material, the bonding force, the size of the crystal atoms, point defects generation energy and migration energy and deep levels, etc.

Table 1 shows a degree of dislocation formation in some different III-V compound semiconductor materials.From this table, it is seen that for almost all of these materials, the larger band gap energy is more likely to form dislocation, such as GaAs and GaP are prone to dislocations, while In-GaAsP materials are not.The mechanism is such that the larger the band gap energy is, the more energy can be provided for the formation of defects.The defects are more conducive for generation and migration.However, according to this theory, InP with a relatively wide bandgap should also be prone to dislocation, but actually it’s not.Bandgap energy alone is not sufficient to explain this behaviour.There are other theories that need further investigation[18-19].

Tab.1 A summary of the easiness of formation of dislocation loops in some III-V compound semiconductors[20]表1 一些III-V族化合物半導體產生位錯的難易程度[20]

Another dominant factor is the weakness of the reconstruction energy between GaAs atoms, which causes the activation energy of dislocation motion in GaAs to be low.The recombination is easily broken or affected by impurities, so dislocation defects are easily formed[20].Besides, other dislocation formation factors include the magnitudes of generation energy and migration energy for point defects and deep levels which are related to such defects as dangling bonds and native point defects, and non-radiative recombination rates at the deep levels, etc[20].

A relatively ideal semiconductor laser materials system is one where active materials are prone to dislocation defects but have sufficient compressive stress to prevent dislocation growth[21].As shown in Fig.2, the Dark Line Defect (DLD) was successfully stopped in GaAs-based lasers by inducing compression strain by introducing 5%-7% indium in quantum wells with a suitable relative thickness.The proportion of indium must be within a suitable range.Too little will not prevent DLD growth,such as in the “No pinning” region in the Fig.2.However, introducing too much indium can lead to lattice mismatch and generate DLD, as shown by the solid line above[19].Kirkbyet al.[22]also showed that indium can prevent dislocation generation and migration even in the absence of compressive strain because the large atomic radius of indium can harden the lattice.Therefore, one might consider adding moderate indium into VCSEL quantum wells to introduce compressive strain and lattice hardening to slow down dislocation formation and migration.

Fig.2 The effect of indium content on laser reliability[19]圖2 銦含量對激光可靠性的影響[19]

3.1.2 Structure design

(1) Oxide layer

The oxide layer problem is a major source of VCSEL failures and is difficult to avoid.As we know, in oxide VCSELs, the oxide layer (AlxOy) is completed by the vapor oxidation of AlAs or Al-GaAs layer containing a very small amount of Ga by the mesa.After AlAs oxidation forms Al2O3, its volume will shrink by about 20%[23-24], which creates greater stress in the oxide layer, especially at the tip.At the same, AlxOyand DBR semiconductor lattice mismatch has a weak binding force and a thermal mismatch in the Coefficient of Thermal Expansion(CTE) at the interface.Improper control of the oxidation process can easily form delamination or cracks between the two interfaces, which is the main source of dislocation defects.

Herricket al.investigated the origin of dislocations in GaAs-based VCSELs[25].The DLD in the device originates from the oxide tip as shown in Fig.3.According to Transmission Electron Microscopy(TEM) work done by others with DLD networks in the active region of the device[26], the DLD may move down from the tip of the oxide layer to the active region below.The direction of propagation may be driven downward by current and form a DLD network as the line dislocations cross the active region[27].

Fig.3 Trace diagram of DLD in a failed VCSEL viewed from the top and side[25]圖3 失效的VCSEL內位錯的示意圖[25]

The material component, thickness of the oxide layer and oxidation process are the main factors affecting the stress after oxidation.Choquetteet al.[24]studied the influence of oxide materials with different Al contents on laser reliability.They found that AlAs oxide layer material is unstable to the rapid thermal cycle and shows excessive strain at the oxide's end during the wet oxidation process, while AlGaAs is stable after oxidation and can provide reliable oxide aperture for VCSEL, as shown in Fig.4.This is because the oxidation reaction rate of Al-GaAs is lower than that of AlAs, making the oxidation process controllable and isotropic, while the mechanical instability inherent in the mesa containing AlAs oxide layer and the greater volume shrinkage resulting from the conversion of the oxide.

Fig.4 Cross-sectional TEM images of different oxide compositions[24].(a) Al0.98Ga0.02As oxide layer;(b) AlAs oxide layer圖4 不同氧化層成分的橫截面TEM（XS-TEM）圖片[24]。(a) Al0.98Ga0.02As 氧化層；(b) AlAs氧化層

Therefore, in order to increase oxide VCSELs'reliability, it is key to reduce the volume shrinkage and stress of the oxide layer, make the oxidation process more stable and controllable through epitaxial design and through an oxidation process control such as changing the composition of the oxide layer's material, reducing the oxide layer's thickness and the oxidation rate etc[28].

(2) Mesa structure

As mentioned above, when performing the selective wet oxidation process, the oxide VCSEL needs to etch a mesa structure before the oxidation process, and this mesa structure is relatively dangerous for the reliability of VCSELs.Firstly, the manufacturing process of the mesa involves etching,cleaning, oxidation, passivation, etc., and the combination of one or more adverse factors in the manufacturing process leads to subtle mechanical damage near the edge of the mesa, which then becomes the source of defects.Secondly, a DBR is alternately grown from AlGaAs material with low Al content and high Al content.The material with high Al content is usually Al0.92Ga0.08As.Therefore, part of the DBR will be oxidized in the actual oxidation process with about 4 μm in thickness, and DBR has many layers, so the cumulative stress is very high as shown below in Fig.5.Delamination or cracking occurs at high enough stresses, and dislocations move from the edge of the oxide to the active region.

Fig.5 Cross-sectional TEM images of an oxide VCSEL mesa[29]圖5 氧化物VCSEL臺面邊緣的XS-TEM照片[29]

Herrick[29]and Helms[30]found a dislocation network in VCSEL failure analysis as shown in Fig.6.The source of dislocation defects is at the edge of the mesa and gradually propagates to the active region, possibly due to excessive mechanical stress introduced by DBR oxide shrinkage at the edge of the mesa.These defects tend to grow slowly towards the active region in a DBR, but once they reach the active region, they grow rapidly, leading to rapid equipment failure.

Fig.6 TEM images showing a tracing of the dislocation network[30]圖6 位錯網絡軌跡的TEM圖像[30]

This problem can be eliminated by inactivating(electro-passivation) the edges of the VCSEL with deep proton implantation to prevent movement of climbing dislocations[31].In addition, Emcore Corporation[30]explored a design without oxides at the mesa edge to eliminate these potential problems,as shown in the original design and experimental design in Fig.7.

Fig.7 Cross-sectional SEM images.(a)Original design.(b)Oxide free design[30]圖7 原始圖(a)和無氧化物圖(b)的截面圖(掃描電鏡)[30]

3.2 Manufacturing

3.2.1 Substrate and epitaxy

The lattice defects, dislocation defects and impurities of the substrate material will seriously affect the lattice quality of subsequent epitaxy[29].Threading dislocations likely caused the defects.Dislocation will climb from the substrate to the epitaxial layer (by the action of recombination-enhanced dislocation motion) and eventually form a large number of dislocation networks in the active region.Failure occurs when the structure of these dislocation networks reaches a certain level[30].At the same time, the defects in the process of epitaxial growth and the lattice mismatch of heterogeneous materials will affect the quality of the device, and the failure will occur due to the current stress,thermal stress and mechanical stress that cannot be released during use.

Therefore, it is extremely important to minimize the occurrence of any defects in substrate and epitaxial growth[31].It is equally important to minimize the epitaxial stress built into the device, because epitaxial stress amplifies the process.Defects can be reduced by strictly checking substrate defects and controlling the quality process of epitaxial growth.Epitaxial growth quality is very important for VCSEL reliability, so some suggestions for controlling the quality process of epitaxial growth are listed.First, during the development process, epitaxial growth temperature, the doping level and gas flow ratio should be optimized.Then in the process of epitaxial growth, the reaction chamber must be clean and the “sacrificed” epitaxial slice is required for collecting the thickness and doping data.After epitaxial growth, each wafer must go through strict epitaxial defects count check and thickness check to remove defective products.Finally, visual inspection is required to check for epitaxial defects,cracks, etc[29].

3.2.2 Wafer fabrication

VCSELs' wafers have many fabrication processes including etching, cleaning, oxidation, passivation, transport, testing, dissociation, packaging,etc.Each process may cause mechanical damage or microcracks on the chip.Itakura Tet al.[32]observed the failed VCSEL through TEM and found that the dislocation Burgers vector was parallel to the direction [101], as shown in Fig.8.From the branch of the dislocation network, it was speculated that the dislocation developed from the lower-left corner of the inner edge of the oxide aperture to the lower right corner of the oxide aperture.Strain or crystal defects introduced during VCSEL manufacturing are considered to be the origin of dislocations.In addition, metal contamination (gold and copper) during the manufacturing process is fatal to a VCSEL.Metal atoms are equivalent to traps that can capture carriers, causing most carriers to recombine non-radiatively, resulting in chip failure.The equipment,process and raw materials should be strictly controlled.

Fig.8 Plan view TEM of failed VCSEL introduced during manufacturing[32]圖8 工藝過程引起失效VCSEL的平面TEM（PV-TEM）圖像 [32]

3.3 External factor

The above summary analyzes the causes of failure in the design and manufacturing of VCSEL devices.The main external factors causing device failure are introduced below, including electrostatic discharge (ESD) or electrical overstress (EOS) impact damage, high temperature, high current and high humidity aging and mechanical damage, etc.

3.3.1 ESD/EOS

Emcore company summarized two modes of VCSEL random failure.The first type of failure is an inherent defect in the design and process of VCSELs.In this failure mechanism, dark line defects originate from the edge of the mesa and spreads to the interior of the emitter hole; the second type is caused by ESD or EOS[30].ESD events occur due to a charge imbalance between the device and another object.Such charges can generate pulses of up to 50 μs, but test instruments with switching transients can generate longer pulse widths for stress testing known as EOS.Oxide VCSELs are a kind of electrostatic sensitive device due to the diameter of oxide aperture usually ranging from 7 μm to 12 μm.VCSEL is easily affected by ESD and EOS, which is a major cause of VCSEL failure.

Many companies in the industry, including AOC[8], Emcore[30], Finisar[33-34], Agilent[35-36], Huawei[37]and Honeywell[38]have conducted many special ESD and EOS studies on the failure mode of oxide VCSEL by LIV, reverse IV, electroluminescence, EMMI, TEM and other failure analysis means.Among these failure analysis methods, a better way to judge whether VCSEL suffers ESD damage failure is to test the reverse IV curve.If compared with good devices, VCSELs with leakage increases and “soft knee” appearances are likely to suffer ESD[35].If regardless of the time and money cost, the TEM method including plan-view TEM(PV-TEM) and cross-sectional TEM (XS-TEM) is the most direct and efficient way to distinguish ESD failure characteristics from other types of failure paths[38-39].The overall characteristics and source location of defects can be determined[33].Therefore,once the failure occurs in the VCSEL, the above methods can be used to confirm whether it is caused by ESD and the specific ESD event.Thus, a targeted investigation and improvement can be efficiently performed.

Matheset al.[8,33]summarized the failure characteristics corresponding to different ESD modes to include the Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM) and EOS, which can be used as a very good base of study for failure analysis by providing more references for similar events in the future and identifying their root causes.Specific PV-TEM and XSTEM results and the characteristics of failure are summarized as follows.

(1) Reverse HBM model

The HBM mode simulates the electrostatic release process of human body contact devices.HBM is the most common and disruptive event for VCSELs.It can be subdivided into forward voltage and reverse voltage shock modes.VCSEL has a lower reverse HBM damage threshold due to power dissipation.The failure characteristics of VCSELs under forward and reverse HBM ESD models were studied in Refs.[40-41].As shown below in Fig.9,the dislocations occur in the interior near the edge of the oxide aperture, and the damage size is approximately a few millimeters in the reverse HBM model.XS-TEM shows that the quantum well melts locally and tangles in the vertical direction, especially in layers with high gallium content.

Fig.9 TEM micrographs of a device subjected to a reverse HBM event[33].(a) Plan-view; (b) cross-section圖9 反向HBM模式損傷的TEM圖片[33]。(a) 平面圖；(b) 截面圖

(2) Forward HBM model

In this mode, dislocations occur at the edge of the oxide aperture where the size is on the order of several hundred nanometers with dislocation density and permanent thermal damage lower than those in the reverse bias HBM mode, as shown in Fig.10.

Fig.10 TEM micrographs of a device subjected to a forward HBM event[33].(a) Plan-view; (b) cross-section圖10 正向HBM模式損傷的TEM圖片[33]。 (a) 平面圖；(b) 截面圖

(3) MM model

The MM mode simulates the electrostatic release process of device and equipment contact.As shown in Fig.11, in the MM mode, dislocations are distributed on both sides of the edge of the oxide aperture and the size is several hundred nanometers.The dislocation extends from above the oxide layer to below the quantum well layer, and there is a higher dislocation density in the high gallium layer.

Fig.11 TEM micrographs of a device subjected to an MM event[33].(a) Plan-view; (b) cross-section圖11 MM模式損傷的TEM圖片[33]。(a) 平面圖；(b) 截面圖

(4) CDM model

The CDM model simulates the accumulation of charge on the device and subsequent discharge when the device comes into contact with other objects.This mode has the shortest duration and the highest pulse intensity of all ESD models.In Fig.12, TEM results show that there is a circular distribution of damage in the oxide layer,which may be related to the shape of the electrode.Dielectric breakdown occurs throughout the oxide layer, sometimes extending to the quantum well region.

Fig.12 TEM micrographs of a device subjected to a CDM event[33].(a) Plan-view; (b) cross-section圖12 CDM模式損傷的TEM圖片[33]。(a) 平面圖；(b) 截面圖

(5) EOS model

EOS usually refers to damage caused by a high current over a long period of time.We used a 45 mA DC current (far beyond the normal operating current of the device) to power up the VCSEL for 960 s.TEM results show that the defects occur in a wide area of the oxide aperture, and the dislocation extends from the top of the oxide layer to the bottom of the quantum well layer as shown in Fig.13.

Fig.13 TEM micrographs of a device subjected to an EOS event.(a) Plan-view; (b) cross-section圖13 EOS模式損傷的TEM圖片。(a) 平面圖；(b) 截面圖

Ref.[42] and our own work have also verified similar experimental results as mentioned above.It can be seen that TEM results of different ESD models are significantly different, which will help to judge the causes of problems and formulate corresponding measures in a more detailed manner.The mechanism of different results is that the oxide layer area of VCSEL is equivalent to a capacitor, and different ESD modes have different impact times,frequencies and intensities, resulting in different defect sizes and different defect positions relative to the oxide layers.

ESD is harmful to components and devices,leading to their failure and interruption of services.It is necessary to prevent ESD in the following four ways.

1.VCSEL design: The oxide aperture is the key parameter that determines the ESD's grade.With the intention of satisfying performance characteristics, increasing the diameter and uniformity of the oxide aperture as much as possible is the way to improve the ESD tolerance level of the device[36,43].

2.Process control: In VCSEL device manufacturing, modules and even equipment manufacturing processes should pay attention to ESD protection and control in every aspect including equipment, operation, process, personnel, environment, etc.Fig.14 below shows the preventive measures taken to prevent ESD generation in the VCSEL manufacturing workshop.

Fig.14 Preventive measures taken to prevent electrostatic discharge in VCSEL workshop[30]圖14 VCSEL 生產車間為防止靜電放電所采取的預防措施[30]

3.Screening: Reverse IV testing and Burn-In accelerated aging can screen out components damaged during VCSEL manufacturing and eliminate early failure samples[36,44].

4.Packaging circuit protection: VCSEL chips are packaged into TO devices or modules, and zener diodes[45]or integrated circuit protection circuits[35]are added to prevent ESD damage to VCSELs.The zener diode protection circuit is shown in Fig.15, where they are connected in inverse bias parallel.The current-shunting effect of Zener diodeis used to protect VCSEL from ESD damage.

Fig.15 VCSEL and Zener Diode package diagram圖15 VCSEL和齊納二極管封裝圖（Zener Diode）

3.3.2 High temperature, current and stress

As we know, high temperature and high current are two main factors affecting a semiconductor laser's life.Defects in the device will generate and expand under high temperatures and high currents until failure.Stress can have the same effect and accelerate aging.Stress comes from issues such as semiconductor lattice mismatching, device processing, and possibly from other nearby dislocations.These external driving stresses provide the energy for defect generation and defect movement,which can accelerate device failure[46].

It was found that temperature, current and stress have the following rules for the generation of defects in semiconductor lasers[46-49]:

1.Thermal stress is the main factor causing dislocation, and dislocation will move and proliferate under stress.Dislocation slip is an intense thermal activation process in GaAs and is almost frozen at temperatures below 300 K.

2.When the current density of a VCSEL reaches a certain value, DLD defects begin to occur in the laser.DLD growth is strongly dependent on driving conditions, so a slight reduction in current will significantly slow down DLD growth.In the absence of current, DLD defects are not observed even at high temperatures or stresses.

3.The dependence of degradation rate on stress and current increases significantly when both stress and current are applied at the same time.Therefore,both injection and stress are necessary for rapid defect growth.

Maeda K[50]and Yonenaga[51]et al.studied the relationship between defect movement velocity and temperature, current, stress and material activation energy in semiconductor devices.The influence of temperature is in line with the Arrhenius equation,and the influence of current and stress on dislocation is a power series relationship, expressed in Eq.(1).

whereτis stress,Iis current,Tis the temperature,Eais the activation energy,kBis the Boltzmann constant,AandBare scaling parameters,mandnare power exponents.

The main measures are to avoid the device working under high current, temperature and stress.One is to increase the heat dissipation capacity of the VCSEL package, and use it with proper process and a high thermal conductivity of submount, etc.An other measure is to specify the maximum current and maximum temperature under normal use conditions.

3.3.3 Humidity

Humidity can also accelerate device aging.Dafincaet al.[52]gave a formula for the influence of temperature, current and relative humidity on device median time to failure.The current and temperature are consistent with the above Eq.(1) and the effect of humidity on median time to failure is exponential, as shown in Eq.(2).

whereRHis relative humidity,ARHis humidity factor, andCis the scaling parameter.

At present, due to the cost and application requirements, VCSELs used in data communication generally adopt non-hermetic packaging.Oxide VCSELs are known to be vulnerable to atmospheric humidity which is a big challenge[53].We need to know the failure mechanisms and to protect against water vapor.Xieet al.[54-56]summarized three main failure modes of oxide VCSELs in a high humidity environment: dislocation growth, semiconductor cracks and optical window surface degradation.The specific failure modes and characteristics are summarized as follows.

(1) Dislocation

Dislocation in oxide VCSELs is the most common failure mode under high temperature and high humidity conditions.As shown in Fig.16, a mass of dislocation networks was observed in the quantum wells region of the samples that failed under 85/85 testing with bias current.The cause of the dislocation is related to the oxide layer, because this failure mode is not observed in the proton injection VCSEL.In addition, this failure mode must be driven by bias current as the same mode does not appear only in high temperature and high humidity conditions.Water vapor corrodes in the oxide layer driven by bias current, resulting in As depletion and excess Ga, which becomes point defects in the form of gaps.When the point defects accumulate to a certain extent to form dislocations, they eventually lead to failure.

Fig.16 Dislocation of oxide VCSEL under humidity corrosion[54-56].(a) PV-TEM; (b)XS-TEM圖16 氧化型VCSEL濕熱腐蝕下的位錯TEM圖片[54-56]。(a)PV-TEM；(b)XS-TEM

(2) Semiconductor crack

This failure mode is also unique to the oxide VCSEL and is not found in implanted VCSELs.The same wafer has no cracks in only high-temperature reliability tests, but the crack rate is very high in the high-temperature and high-humidity test.As shown in Fig.17, semiconductor cracks begin at the oxide tip.Due to moisture accumulation in the oxide layer and the thermal gradient of bias current in high-temperature and high-humidity tests, cracks appear and expand in the oxide tip where stress is high.Due to changes in the manufacturing process, devices with high built-in stress are prone to this kind of cracking.

Fig.17 Semiconductor crack of oxide VCSELs under humidity corrosion[54-56].(a) Case1; (b) Case2圖17 氧化型VCSEL濕熱腐蝕下的半導體裂紋[54-56]。（a）情形1；（b）情形2

(3) Aperture surface degradation

The degradation of the aperture surface during high temperature and humidity may be due to a reaction between surface GaAs, moisture and contaminants (if any), as shown in Fig.18.Atmospheric cleanliness can cause this failure mode, which is accelerated by bias currents.This failure mode is not unique to oxide VCSELs.

Fig.18 SEM of aperture surface degradation of oxide VCSEL after humidity corrosion[54-56]圖18 氧化型VCSEL濕熱腐蝕下的光窗表面退化SEM圖片[54-56]

Dafinca[52]and Herrick[25]studied the mechanism of moisture corrosion leading to VCSEL failure,as shown in Fig.19.Moisture corrosion occurs near the oxide tip, leading to cracking.Cracking near the oxide tip causes dislocations to move down to the active region, which usually takes years to grow.Once it infiltrates the active area, a DLD network grows rapidly in the active region and the device fails completely within minutes.

Three protection measures are proposed when a VCSEL works in a non-hermetic environment to protect against the failure modes and mechanisms.

Fig.19 Schematic diagram of VCSEL corrosion failure mechanism[52]圖19 VCSEL腐蝕失效機制示意圖[52]

Firstly, chips' “extrinsic” design is addressed.A protective passivation layer (coat) should be deposited on the outside of the chip to prevent water vapor from eroding into the inside of the device through deposition methods including Plasma Enhanced Chemical Vapor Deposition (PECVD) and Atomic Layer Deposition (ALD).The specific materials of the protective film may be Al2O3, SiO2,AlN, etc[57].At the same time, the thickness of the protective film should be well controlled: too thin cannot properly protect the chip and too thick will cause too much stress and affect its reliability.

Secondly, chips' “intrinsic” design is addressed.As mentioned above, the chip should have a strong oxide layer design.By controlling the thickness of the oxide layer and the oxidation process conditions,reduces the internal stress of the chip, especially the shrinkage stress after oxidation, increases the atomic bonding density of the oxide layer, and slows down the water vapor reaction inside the device.

Thirdly, the chip must be externally protected to create the effect of “hermetic” packaging.As shown in Fig.20, the chip can be coated with an appropriate thickness of the epoxy resin to prevent water corrosion[25,58-59].

Fig.20 Coating epoxy resin to protect the VCSEL[25]圖20 使用環(huán)氧樹脂對VCSEL進行保護[25]

3.3.4 Mechanical damage

Damage caused by external stress, such as cracks and scratches, can become the source of dislocation formation[32,60].For oxide VCSEL, the mechanical damage propagating inward from the edge of the mesa is always a risk[61].When mechanical damage is introduced from outside, dislocation defects will continue to grow from the source of the damage point in the subsequent use process, and finally cause failure[11].Fig.21 shows an example of how a scratch can cause DLD.The two photos on the left show the SEM images of the scratches.The central image shows the electroluminescence (EL)of the received failed VCSEL.The image on the right shows the DLD moving from the bottom left to the top right.After a few minutes at 10 mA, the DLD continues to grow to the right[11].

Fig.21 Example of DLD caused by scratch[11]圖21 刮傷引起DLD的示例[11]

Typically, a strict 100% visual inspection is carried out to remove damaged parts during the process, or the chip is designed to prevent mechanical damage from spreading to the active region by wetetching grooves of appropriate width, or electrically passivating the mesa edge material.

3.4 Some case study

In order to serve readers with a more comprehensive failure analysis, in addition to the VCSEL production design company and the research achievements of academic literature, we also collected a set of failure mode summary results.Three typical failures in accelerated aging validation are shown below for supplementary reference.The failure causes include epitaxial defects, oxidation anomalies, mesa oxidation stress, ESD and DLD.

(1) Case 1

Fig.22 shows TEM images of samples that failed during high temperature and high current testing.It can be seen that there are two main failure characteristics: abnormal oxidation at the edge of the oxide layer and epitaxial dark spot defects in the active region.The causes of these two problems are related to the quality of the oxidation process and epitaxial growth, respectively.

Fig.22 TEM images of Case 1.(a)Overall PV-TEM.(b)Partial enlargement in the (a) dotted box.(c)XSTEM in the (b) dotted box圖22 案例1失效樣品的TEM圖片。（a）整體PV-TEM；（b）局部放大圖；（c）XS-TEM圖片

(2) Case 2

Fig.23 shows TEM results of VCSEL failure after aging for 500 h at a high temperature and high current.Fig.23(a) shows a DLD network diagram.The origin of dislocation is the oxidized mesa edge which gradually moves to the active region as it ages.As shown in Fig.23(c), cross-sectional TEM results, the thickness of the oxide layer is about 100 nm at the edge of the mesa, far beyond the normal thickness of the oxidation tip by about 20 nm.This is the root cause of failure due to the oxide layer being too thick at the mesa's edge.

Fig.23 TEM image of Case 2.(a)Overall PV-TEM.(b)Partial enlargement in the (a)dotted box.(c)XSTEM圖23 案例2失效樣品的TEM圖片。（a）整體PV-TEM；（b）局部放大圖；（c）XS-TEM

(3) Case 3

The TEM results of Fig.24 show failure samples in high temperature and high humidity(85/85) tests.The failure mode is that there are many defects at the edge of oxide aperture, which are especially severe at the oxidation corner area where stress is largest.At the same time, many DLD networks are generated with oxide aperture defects as the starting point, which is consistent with Krueger's research results.ESD failure characteristics are usually accompanied by DLD dislocations.If the device continues to work or age after ESD damage, DLD will diffuse and develop at the damaged location[36].

Fig.24 PV-TEM images of Case 3圖24 案例3失效樣品的PV-TEM圖片

4 Conclusion

The reliability of the oxide VCSEL is closely related to the materials system, device design, substrate and epitaxial, process quality and external factors.Among these factors, the materials system determines the degree of defect generation, VCSELs made of GaAs/AlGaAs materials are also vulnerable to dislocations.The oxide layer and etched mesa structure introduce an inherent defect source,and most of the failure modes are associated with oxidation stress.Substrate, epitaxy and the manufacturing process determine the density of defects in the device.External factors introduce the source of defects and also can provide the driving force for the generation and multiplication of defects.Among them, VCSELs are susceptible to ESD stress and in non-hermetic applications, humidity and heat corrosion are also major factors of VCSEL failure.

This paper summarizes and analyzes the common failure modes and causes in oxide VCSELs,and puts forward corresponding improvement suggestions and preventive measures.It can provide a good reference for VCSEL practitioners to help identify the source of the problems, dig out the root causes and implement appropriate measures for improvement.In such a way, the high reliability and low failure rate of the VCSEL devices can be improved gradually in field applications.It has important practical engineering significance.More comprehensive and accurate failure causes and mechanism models need further study in the future.

——中文對照版——

1 引 言

垂直腔面發(fā)射激光器（Vertical Cavity Surface Emitting Laser，VCSEL）擁有閾值低、功耗低、速率高、易于集成和成本低等優(yōu)點，是短距離數(shù)據(jù)通信的核心光源，其中絕大多數(shù)采用GaAs體系材料，在850 nm波長下發(fā)光，主要用于數(shù)據(jù)通信和光學跟蹤應用[1-4]。

可靠性作為半導體激光器能夠長期使用的一個關鍵的指標，對應用非常重要，是器件開發(fā)設計和應用的核心問題[5-6]。隨著設計能力和工藝水平的提升，以及采取了廣泛的預防措施和篩選措施，目前半導體激光器的現(xiàn)場故障率達到了10 ppm /年[7-8]，但是如果沒有進行適當?shù)钠骷O計、制造和使用，將導致器件具有較高的故障率。而且VCSEL每年發(fā)貨數(shù)量龐大[9]，即使低的失效率也會有絕對數(shù)量的不良品，當這些故障聚集在擁有數(shù)千條鏈路的大型數(shù)據(jù)通信中心時，系統(tǒng)的故障率仍可能涉及每年多次計劃外故障，同時在數(shù)據(jù)通信應用中對器件的使用壽命一般比較長，通常在10年以上[10]，這對VCSEL器件的可靠性提出了較高的要求。對于以GaAs材料為基礎的氧化限制型VCSEL，由于器件材料和結構設計的固有原因，會有潛在的可靠性問題，受到工業(yè)界的極大關注[11-13]。

因此，本文以目前商業(yè)化應用最廣的氧化限制型850 nm VCSEL為對象[9]，從器件設計、加工制造和外界因素等三個方面詳細闡述導致VCSEL失效的常見原因，總結了失效的模式及失效機理，并給出一些預防措施和改善建議，通過研究VCSEL的失效模式及機理，可以為VCSEL從業(yè)人員提前預防失效的發(fā)生，當問題發(fā)生時也可以作為一個參考，從而更加快速有效地了解問題產生的根本原因，并進行合理的改進，以提升器件的可靠性。

2 VCSEL 結構

氧化型VCSEL 的結構是由襯底（substrate）、上下布拉格反射鏡(DBR)、量子阱有源區(qū)（active layer）、氧化限制層（oxide layer）、上下電極（contact）組成，光輸出方向垂直于晶圓表面，激射波長為850 nm。氧化型VCSEL的器件結構示意圖如圖1所示。襯底一般是n型摻雜GaAs材料，DBR是由兩種不同折射率材料（不同Al含量的AlGaAs）交替生長而成，有源區(qū)由GaAs/AlGaAs或AlGaAs/InGaAs多量子阱組成。氧化限制層是通過對含高Al成分的AlGaAs或者AlAs材料進行選擇性濕法氧化得到Al2O3結構，氧化層厚度一般為20～30 nm，氧化后的孔徑一般為7～12 μm，能夠對電流和光場起到有效的限制作用，從而可以有效降低閾值電流和光損耗，提高VCSEL的功率轉換效率，大大提高了VCSEL的性能[14-15]。

3 常見失效原因及分析

3.1 VCSEL 設計

3.1.1 材料體系

由于GaAs和AlGaAs材料的晶格匹配，能帶范圍決定了可以在850 nm范圍內發(fā)光，同時兩種材料具有較大的折射率差，器件可以在較小的DBR厚度下獲得較高的反射率和優(yōu)異的性能，所以目前商業(yè)化廣泛應用的氧化型VCSEL由GaAs/AlGaAs材料制備而成。但是研究發(fā)現(xiàn)GaAs/Al-GaAs化合物半導體材料容易形成位錯[17]，這可能是由于材料的能帶間隙、晶體原子結合力、原子尺寸大小、缺陷能級及點缺陷的形成能和遷移能等因素導致的。表1為一些Ⅲ-Ⅴ族化合物半導體材料形成位錯的難易程度。可以看出，具有較大能帶間隙能的材料，如GaAs和GaP容易形成位錯，而帶隙能較小的InGaAsP材料則不會，這是由于能帶間隙能越大，可以提供給缺陷形成的能量就越大，因此缺陷越容易產生和運動。然而，帶隙相對較寬的InP卻不容易產生位錯，這說明僅從帶隙能角度并不能充分解釋，還有其他機理有待進一步研究[18-19]。

另外，GaAs原子間的重建能量相對較弱，GaAs中位錯運動的活化能較低，而且重組很容易被雜質破碎或受雜質影響，因此容易形成位錯缺陷[20]。此外，位錯形成的影響因素還包括與懸空鍵和原生點缺陷等缺陷相關的點缺陷和深能級的生成能和遷移能的大小，以及深能級的非輻射復合率等。

對于半導體激光器的一種較為理想的材料體系是有源區(qū)材料雖然容易產生位錯缺陷，如本文研究的GaAs基VCSEL，但是有源區(qū)材料具有足夠的壓縮應力可以阻止位錯生長[21]。如圖2所示，在適當?shù)牧孔于搴穸认?，通過在量子阱中引入5%～7%的銦，誘導壓縮應變，成功地在GaAs基激光器中阻止了位錯（Dark Line Defect，DLD）產生。銦元素的比例有個合適的范圍，太少起不到阻止DLD生長的作用，如圖2虛線左側部分[19]。然而，引入過多的銦會導致晶格失配而產生DLD，如圖2中實線右上部分。Kirkby[22]和其他人也指出，即便在沒有壓縮應變的情況下，銦也能阻止攀爬和下滑。這是因為In有較大的原子半徑，可以使晶格硬化，阻止位錯的產生和遷移。因此，可以考慮在VCSEL有源區(qū)材料內增加適量的銦以引入壓縮應變和晶格硬化來減緩位錯的形成。

3.1.2 結構設計

(1) 氧化層

氧化問題是VCSEL失效的主要原因，而且是一個很難避免的難題。眾所周知，氧化型VCSEL中，由于氧化層（AlxOy）是由AlAs或含有極少量Ga的AlGaAs層經過臺面水汽氧化得到的，AlAs氧化形成AlxOy時體積會有約20%的收縮[23-24]，這樣就會在氧化層，尤其尖端，形成較大的應力，同時由于氧化后形成的氧化鋁和DBR半導體晶格不匹配，結合力弱，以及熱膨脹系數(shù)（CTE）不匹配等，如果氧化工藝控制不當很容易在兩者界面之間形成分層或者裂紋[23]，成為位錯缺陷形成的主要源頭。

Herrick等人研究了GaAs基 VCSEL的位錯的起源[25]，如圖3所示，認為器件內的線DLD起源于氧化物尖端?；谄渌藢ζ骷性磪^(qū)內有DLD網絡的透射電子顯微鏡（TEM）工作可知[26]，認為線位錯可能從氧化層尖端向下移動到下面的有源區(qū)，傳播方向可能是受到電流向下的驅動[27]，并在線位錯穿過有源區(qū)時形成DLD網絡。

氧化層的材料組分、厚度和氧化工藝等是影響氧化后應力的主要因素。Choquette等人[24]對不同Al含量氧化層材料對可靠性的影響進行了研究，在濕法氧化過程中，AlAs氧化層材料對快速熱循環(huán)不穩(wěn)定，在氧化端表現(xiàn)出過度的應變，而AlGaAs材料氧化后則是穩(wěn)固的，可以為VCSEL提供可靠的氧化孔，如圖4所示。這是因為AlGaAs的氧化反應速率比AlAs的低，故其氧化過程可控、各向同性，而包含AlAs氧化層的臺面中存在固有的機械不穩(wěn)定性以及轉換氧化物后更大的體積收縮。因此，可以通過改變氧化層材料成分、降低氧化速率和減少氧化層厚度等方式來降低氧化層的應力和減小體積收縮，增加VCSEL可靠性[28]。

(2) 臺面(mesa)結構

氧化型VCSEL在選擇性濕法氧化工藝時，需要蝕刻出一個臺面柱狀（mesa）結構，然后再進行氧化工藝，而該結構設計對器件的可靠性來說是比較危險的。一是器件臺面制作過程中涉及蝕刻、清洗、氧化和鈍化等工序，加工過程中一種或者多種不利因素的組合導致臺面邊緣附近細微的機械損傷，而后成為缺陷的源頭；二是DBR是由低Al含量和高Al含量的AlGaAs材料交替生長而成的，高Al含量的材料通常是Al0.92Ga0.08As，因此在實際氧化過程中也會有部分被氧化，一般為4 μm左右，而且DBR有很多層，所以累積應力非常高，如圖5所示。當應力足夠高而引起分層或者裂紋時，位錯會從氧化物的邊緣向有源區(qū)移動。

Herrick[29]和Helms[30]對失效的VCSEL分析發(fā)現(xiàn)這是由于DBR氧化物收縮而引入過度的機械應力導致的失效，如圖6所示的位錯網絡，圖中TEM圖像顯示位錯可疑的起點在靠近臺面氧化物的邊緣，并逐漸向發(fā)光區(qū)傳播。這些缺陷在DBR中向有源區(qū)域緩慢增長，一旦它們到達有源區(qū)域，就會迅速增長，從而導致設備快速失效。

對于前面所討論的臺面?zhèn)让鏁胁糠諨BR氧化引入應力或分層的問題，可以通過深質子植入方法使VCSEL的邊緣失去活性（電鈍化）來消除，以防止攀爬位錯的運動[31]。另外，Helms等人[30]探索一種在臺面邊緣沒有氧化物的設計，以消除這些潛在的問題，原始設計和實驗設計如圖7所示。

3.2 加工制造

3.2.1 襯底和外延

襯底材料自身的晶格缺陷、位錯缺陷和雜質會嚴重影響后續(xù)外延的晶格質量[29]，位錯會從襯底層向外延層中攀爬（通過非輻射復合增強缺陷攀移運動的作用），最終在有源區(qū)中形成大量的位錯網絡結構。當這些位錯網絡結構達到一定程度的時候，就會產生失效[30]。

同時，外延生長過程中的缺陷以及異質材料晶格失配問題都會影響器件的質量，在使用過程中出現(xiàn)無法釋放的電流應力、熱應力和機械應力而產生失效。

因此，襯底和外延生長中盡量減少任何缺陷的發(fā)生是極其重要的[31]。同樣重要的是盡量減少器件內建的外延應力，因為外延應力會放大這一過程。通過嚴格檢查襯底缺陷和控制外延生長的質量，可以減少缺陷的產生。對于外延生長質量的控制，首先，在開發(fā)過程中應優(yōu)化外延生長溫度、摻雜水平和氣體流量比等；然后在外延生長過程中，反應室必須是干凈的，需要用陪片來收集其余外延片的厚度和摻雜等數(shù)據(jù)；外延生長完成后，每片晶片都必須經過嚴格的外延缺陷計數(shù)檢查和厚度檢查，剔除不良產品。最后，需要目視檢查外延缺陷、裂紋等[29]。

3.2.2 工藝環(huán)節(jié)

由于VCSEL的制作工藝流程較多，涉及蝕刻、清洗、氧化、鈍化、轉運、測試、解離、封裝等工序，每個工序都可能會對芯片造成機械損傷，微裂紋等。Itakura等人[32]通過TEM觀察失效的VCSEL發(fā)現(xiàn)位錯柏式矢量平行于[101]方向，如圖8所示，從位錯網絡分支來看，推測位錯是從氧化孔內緣左下角附近開始向氧化孔右下角發(fā)展的。在VCSEL制造過程中引入的應變或晶體缺陷被認為是位錯的起源。

另外，工藝制造環(huán)節(jié)金屬（金、銅）污染對于VCSEL是致命的，金屬原子在半導體激光器中相當于陷阱，會捕獲載流子，從而導致大部分載流子以非輻射方式復合，最終導致芯片失效。因此，要對使用的設備、工藝過程和原材料進行嚴格管控。

3.3 外部因素

上述總結分析了氧化型VCSEL器件本身在設計和制作中產生失效的原因，下面從應用過程的角度分析一些主要的外在因素引起失效的機理，包括靜電放電（ESD）或者電過應力（EOS）沖擊損傷，高溫、高電流及高濕的老化和機械損傷等。

3.3.1 ESD/EOS

Emcore公司對VCSEL的隨機失效總結出兩種模式，第一類失效在VCSEL的設計和工藝中的固有缺陷，在這種破壞機制中，暗線缺陷起源于臺面的邊緣，并向發(fā)射孔的內部傳播。第二類是由于ESD或EOS引起的[30]。ESD事件是由于器件和另一個物體之間的電荷不平衡而發(fā)生的，這種電荷產生的脈沖時間較短，具有開關瞬變的測試儀器可以產生更長的脈沖寬度電流沖擊，這種稱為EOS。VCSEL是一種靜電敏感器件，氧化型VCSEL的氧化孔直徑一般為7 μm至12 μm，使得VCSEL容易受到ESD和EOS的影響，是VCSEL失效的一大主要原因。

很多行業(yè)內的公司，包括AOC[8]，Emcore[30]，F(xiàn)inisar[33-34]， Agilent[35-36]， Huawei[37]和Honeywell[38]等，對VCSEL ESD的失效模式進行了許多專項的研究。對器件人為引入人體模式（HBM）、機器模式（MM）、組件充電模式（CDM）等不同ESD模式和EOS沖擊，然后通過測試LIV、反向IV、電致發(fā)光（EL）、發(fā)光顯微鏡（EMMI）和TEM等進行表征，建立不同ESD模式和失效特征的聯(lián)系，從而建立一個ESD失效案例庫以在后續(xù)發(fā)生失效時進行比照參考。而對于判斷VCSEL是否遭受到ESD損傷失效比較好的分析方式，一是通過測試反向IV曲線，如果與好的器件相比漏電增加和出現(xiàn)“soft knee”的特征，很可能是遭受到了ESD[33]，但是這并不能直接確定ESD就是失效的根本原因。然而，如果不考慮時間和金錢成本，通過TEM方法（包括PV-TEM和XS-TEM）是最直接有效的方式，是區(qū)分ESD故障與其他類型故障路徑的最佳方法之一[38-39]，可以判斷缺陷的整體特征和發(fā)生源頭位置等信息[36]。因此，一旦VCSEL出現(xiàn)失效，可以通過上述方法確認是否是ESD導致，以及具體是哪種ESD模式，從而有針對性地進行排查和改善。Mathes等人[8,33]總結出了不同ESD模式對應的PV-TEM和XS-TEM特征，具體失效TEM結果和特征總結如下。

(1) 反向HBM模式

HBM模式模擬人體接觸器件的靜電釋放過程，對于VCSEL來說，HBM是最常見和最具破壞性的模式。這里分為正向電壓和反向電壓沖擊模式，由于功率耗散的原因，VCSEL具有較低的反向HBM損傷閾值。其中，文獻[40-41]具體研究了氧化物VCSEL在正向和反向HBM ESD模型下的失效特征。圖9的TEM結果顯示，反向HBM模式下位錯發(fā)生在靠近氧化孔徑邊緣的內部，損傷尺寸大小為毫米量級。XS-TEM顯示量子阱局部會融化，并發(fā)生在垂直方向。橫向位錯會纏結，特別是在含鎵量高的層中。

(2) 正向HBM模式

如圖10所示，這種模式下位錯發(fā)生在氧化孔徑邊緣，大小在數(shù)百納米量級。位錯密度和永久性熱損傷比反向偏置HBM模式低。

(3) MM模式

MM模式模擬設備和器件接觸的靜電釋放過程。如圖11所示，這種模式沖擊下位錯分布在氧化物孔邊緣的兩側，大小為數(shù)百納米量級。位錯從氧化層上方延伸到量子阱層下方，在高含鎵層中有更高的位錯密度。

(4) CDM模式

CDM模式是模擬操作不當時，器件上積累電荷，隨后當器件和其他物體接觸時放電的過程。這種模式的持續(xù)時間最短，脈沖強度最高。圖12的TEM結果顯示在氧化層會形成圓環(huán)形分布的損傷，這可能和電極的形狀有關。整個氧化層會出現(xiàn)介電擊穿現(xiàn)象，有時延伸到QW層。

(5) EOS模式

EOS通常是指長時間大電流的損傷，本文采用45 mA直流電流（遠超過器件正常工作電流）持續(xù)960 s對VCSEL進行加電模擬，圖13的TEM結果顯示缺陷發(fā)生在整個氧化層較廣的區(qū)域，氧化層和DBR半導體層在高電流應力下出現(xiàn)分層現(xiàn)象。

對于以上幾種模式，文獻[42]和本課題組都得出了相似的實驗結果?？梢钥闯?，損傷基本上分布在氧化孔周圍，不同ESD模式的TEM結果會有明顯的不同，這將有助于更加準確地判斷問題產生原因并制定相應措施。產生不同結果的原因可認為是VCSEL的氧化層區(qū)域等效為一個阻抗，而不同ESD模式的沖擊時間、頻率和強度不同從而導致?lián)p傷點相對于氧化層的位置以及缺陷大小具有不同的特征。

ESD對器件和設備的危害比較大，會顯著降低器件的使用壽命或者直接導致器件和設備失效而中斷業(yè)務，因此，對ESD的防護是有必要的，可以通過如下方式減少VCSEL在應用過程中的失效：

（1）器件設計：VCSEL中的氧化孔徑是決定ESD等級的關鍵參數(shù)，在滿足性能特性的情況下，盡可能增加氧化孔徑的直徑和均勻度以提高器件耐受ESD等級[36,43]；

（2）過程管控：在VCSEL器件制造，包括模塊到設備制造過程中的每個環(huán)節(jié)（設備、操作、過程、人員、環(huán)境等）注重ESD的防護和管控，圖14顯示了VCSEL生產制造車間內為了防止靜電產生所采用的預防措施。

（3）篩選不良：反向IV測試和burn in能夠篩選出在VCSEL制造過程中損壞的器件，剔除早期失效樣品[36,44]，在器件正式投入使用前需要經過上述方法進行100%篩選。

（4）封裝電路保護：將VCSEL芯片封裝到TO器件或者模塊中，增加齊納二極管[45]或者IC保護電路等都可以防止ESD損傷VCSEL[35]。圖15是VCSEL和齊納二極管（Zener Diode）封裝圖，兩者電極反向并聯(lián)，利用齊納二極管的分流作用保護VCSEL免受ESD損傷。

3.3.2 溫度/電流/應力

眾所周知，激光器在高溫和高電流驅動下會加速老化，溫度和電流是影響壽命的兩個主要因素，器件內的缺陷會在高溫高電流“催化”下產生、擴展直至失效。應力（例如來自半導體晶格常數(shù)失配、器件加工的應力，也可能是來自附近其他位錯的應力）也會有同樣的效果。這些外在的驅動應力為缺陷產生以及缺陷移動提供了能量，會加速器件失效[46]。

研究發(fā)現(xiàn)[46-49]，溫度、電流和應力對半導體激光器內缺陷的產生有如下規(guī)律：

（1）熱應力是位錯產生的主要因素，在應力的作用下，位錯會發(fā)生運動和增殖。位錯滑移在砷化鎵中是一個強烈的熱激活過程，在300 K溫度以下幾乎凍結。

（2）在VCSEL器件工作過程中，當電流密度達到一定值時，在激光器中就開始產生 DLD 缺陷。DLD的增長強烈地依賴于驅動條件，電流的略微降低會顯著減緩DLD的增長。在沒有電流的情況下，即使加的溫度或者應力很高也不會觀察到DLD缺陷。

（3）在同時施加應力和電流的情況下，退化率對應力和電流的依賴性顯著增加。因此，注入(即非輻射復合能源)和應力對缺陷的快速生長都是必要的。

Maeda K[50]和Yonenaga[51]等人研究半導體器件內缺陷的移動速度和溫度、電流、應力以及材料的激活能等的關系，溫度的影響關系符合Arrhenius方程，電流和應力對位錯的影響是冪級數(shù)的關系，表達公式如下。

式中，τ為應力，I為電流，T為溫度，Ea為激活能，kB為玻爾茲曼常數(shù)，m，n為冪指數(shù)，A和B為比例參數(shù)。

主要措施是避免器件在大電流、高溫高應力下工作，一是增加VCSEL的封裝散熱能力，二是規(guī)定好正常使用條件下的最大電流和最高溫度。

3.3.3 濕度

濕度也可加速器件老化，Dafinca[52]等人給出溫度、電流和相對濕度對器件壽命（Median time to failure）的影響公式，其中電流和溫度的影響關系同公式(1)，濕度對壽命的影響符合指數(shù)關系，具體如表達式(2)所示：

其中，f(I)、f(T)、f(RH)分別為電流、溫度和相對濕度有關的函數(shù)，C為和電流有關的系數(shù)，Ea為激活能，RH為相對濕度，ARH為濕度因子。

目前，從成本和應用等角度考慮在數(shù)據(jù)通信中使用的VCSEL一般采用非氣密封裝，但是氧化型VCSEL很容易受到濕氣的影響[53]。因此，器件需要有水汽防護能力，這對VCSEL是一個比較大的挑戰(zhàn)。Xie等人[54-56]總結出3種主要氧化型VCSEL在高濕環(huán)境下的失效模式：位錯增長，半導體裂紋和光窗表面退化，具體失效模式和特征總結如下。

(1) 位錯

在氧化型VCSEL中，位錯是高溫高濕條件下最為常見的一種失效模式，如圖16所示，在高溫高濕加偏置電流條件下，可觀察到失效樣品在量子阱區(qū)域有大量的位錯網絡。區(qū)別于ESD類型故障，此種失效特征在氧化層尖端沒有任何損傷，僅在量子阱區(qū)域存在位錯。這為區(qū)分這兩種類型提供了一個重要的方法。同時，正向偏置電阻和反向漏電的增加是這種失效模式的額外特征[35]。

位錯的發(fā)生和氧化層有關系，因為在質子注入VCSEL中沒有觀察到這種失效模式。而且出現(xiàn)此種失效模式必須要有偏置電流的驅動，只在高溫高濕條件下沒有出現(xiàn)相同模式的失效。在偏置電流驅動下，水汽在氧化層中發(fā)生腐蝕反應，導致As耗盡而留下過量的Ga，過量的Ga以間隙的形式成為點缺陷，點缺陷積累到一定程度形成位錯，最終導致失效。

(2) 半導體裂紋

這種失效模式也是氧化型VCSEL獨有的，質子注入型VCSEL沒有。相同晶片在沒有濕度的高溫可靠性實驗中沒有出現(xiàn)裂紋，在高溫高濕試驗中裂紋發(fā)生率卻很高，如圖17所示。裂紋起源于氧化尖端，這是由于在高溫高濕試驗過程中，氧化層中的水分積累以及偏置電流存在熱梯度，在應力較大的氧化尖端出現(xiàn)裂紋并擴展。由于制造工藝的變化，具有較高內置應力的器件容易發(fā)生這種開裂。

(3) 光窗表面退化

高溫高濕期間，光窗表面退化可能是由于表面砷化鎵、水分和污染物(如果有的話)之間的反應，如圖18所示。大氣清潔度可能導致這種故障模式，偏置電流下會加速這種故障模式，這種失效模式不是氧化物VCSEL所獨有的。

Dafinca[52]和Herrick[25]研究了濕氣腐蝕導致VCSEL失效的機理，如圖19所示，濕氣腐蝕在氧化尖端附近發(fā)生，從而導致開裂，氧化尖端附近的開裂導致位錯向下移動到活性區(qū)域，這通常需要生長數(shù)年的時間。一旦它滲透到有源區(qū)域，有源區(qū)域的DLD網絡就會迅速增長，并在幾分鐘內使器件完全失效。

從失效模式和機理可以看出，VCSEL芯片工作在非氣密環(huán)境下，需要三方面的防護措施。第一，芯片“外在”設計，要在芯片外面沉積一層保護鈍化層（“coat”），防止水汽進入到器件的內部。沉積方法有等離子體化學氣相沉積（PECVD）、原子沉積（AlD），保護膜的具體材料可能是Al2O3、SiO2、AlN等[57]。同時，保護膜的厚度也要控制好，太薄起不到保護作用，太厚會造成應力過大，影響可靠性。第二，如上所述芯片“內在”的氧化層強壯設計，通過氧化層的成分、厚度和氧化工藝條件控制減少芯片的內在應力，尤其是氧化后的收縮應力，增加氧化層的原子結合致密度，減緩器件內部侵入的水汽反應。第三，通過外界保護，營造出“氣密”封裝的效果，如圖20所示，可以在芯片外面涂上一定厚度的環(huán)氧樹脂阻止水汽的腐蝕[25,58-59]。

3.3.4 機械損傷

外界應力造成的裂紋、劃痕等損傷會成為位錯缺陷形成的源頭[32,60]，對于氧化型VCSEL，如上所述，從mesa邊緣向內傳播的刻痕損傷一直是一個風險[61]。當器件發(fā)生機械損傷后，在隨后的使用過程中位錯缺陷會繼續(xù)生長，最后引起失效[11]。圖21顯示了一個刮傷（scratch）如何引起DLD的。左邊兩張照片顯示了劃痕的SEM圖像，中心圖像顯示了接收到的失效VCSEL的電致發(fā)光(EL)， DLD從左下移動到右上。右邊圖片顯示的是在10 mA下放置幾分鐘后DLD繼續(xù)向右生長[11]。

通常，在工藝環(huán)節(jié)通過嚴格的100%目檢來挑除損傷器件，或者在設計上通過濕法蝕刻出適當寬度的溝槽，或電鈍化mesa邊緣的材料來避免機械損傷造成的缺陷傳到有源區(qū)內。

3.4 案例分析

除了上述VCSEL生產設計公司和學術文獻的研究成果，本課題組也積累了一定的失效模式案例，包括不同ESD模式沖擊后的失效特征，以下加速老化驗證過程中3個典型的失效案例作為補充參考。這些失效原因主要包括外延缺陷，氧化異常，mesa氧化應力，ESD和DLD。

(1) 案例1

圖22為在高溫高電流長時間試驗時失效的樣品TEM圖片，從圖中可以看出，其有兩個主要的失效特征，一是氧化層邊緣有異常氧化問題，二是有源區(qū)內有外延黑點缺陷。導致這兩個問題的原因分別和氧化工藝和外延生長質量有關。

(2) 案例2

圖23為高溫高電流500 h老化后失效VCSEL的TEM結果，圖片顯示了DLD網絡圖，位錯的起源為氧化臺面邊緣，其在老化過程中逐漸向有源區(qū)移動，當位錯網絡達到一定程度時導致器件失效。如圖23（c）XS-TEM結果所示，氧化層在臺面邊緣較厚，約為100 nm，而氧化尖端厚度約為20 nm，為正常厚度，臺面邊緣過厚的氧化層會形成較大的應力，成為位錯缺陷的源頭，是失效的原因。

(3) 案例3

圖24的TEM結果為高溫高濕（85/85）測試中的失效樣品，失效現(xiàn)象為氧化孔邊緣出現(xiàn)晶格融化的永久熱損傷，在應力最大的氧化邊角區(qū)域缺陷尤其明顯，同時，以氧化孔邊緣缺陷為起始點，生成很多DLD網絡，這與Krueger的研究結果一致，ESD的失效特征通常伴隨DLD位錯，ESD損傷后，器件繼續(xù)工作或者老化，就會在損傷的位置擴散發(fā)展為DLD[36]。

4 結束語

氧化型VCSEL的可靠性和器件的材料體系、結構設計、襯底及外延質量、工藝過程和外界因素都有密切關系。在這些因素中，器件的材料體系決定了器件產生缺陷的難易程度，對于GaAs/AlGaAs材料體系的VCSEL來說，較為容易產生位錯缺陷；氧化型VCSEL的器件結構中氧化層和蝕刻臺面結構引入了固有的缺陷源頭，所有失效模式大都和氧化層的應力相關；襯底、外延和器件工藝決定了器件內缺陷的密度水平；外界因素可以引入缺陷的源頭，也可提供缺陷產生和擴展增殖的驅動力，其中，VCSEL是ESD敏感型器件，很容易受到ESD的損傷發(fā)生失效，而在非氣密性應用下濕熱腐蝕也是VCSEL失效的一大因素。

本文對導致VCSEL失效的常見模式及其機理進行了總結歸納和分析，并提出對應的改善建議和預防措施。為VCSEL從業(yè)人員提供參考，有助于防止失效的產生，或者當問題發(fā)生時能夠快速有效地確定問題的來源、挖掘出問題的根本原因并實施恰當?shù)母纳拼胧?，從而逐步提升器件的應用可靠性、降低使用過程中的失效率，具有重要的實際工程意義。未來需要進一步研究更全面和準確失效原因和機理模型。